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Senior AI ASIC Design Engineer: End-to-End RTL & Silicon
Job Description & How to Apply Below
M Partners is looking for a Senior ASIC Design Engineer to lead the end-to-end design of critical AI ASIC subsystems, focusing on efficiency and performance. The role requires a minimum of 7 years of experience in RTL design and ASIC development, with strong proficiency in Verilog/System Verilog. This position involves working closely with silicon architects and firmware teams.
Join a dynamic environment where your contributions will drive advancements in AI workloads.
#J-18808-LjbffrPosition Requirements
10+ Years
work experience
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