Senior Researcher in SoC Architecture; Wireless Technologies

(Senior) Researcher in SoC Architecture (Wireless Technologies)

Huawei’s vision is to enrich lives through communication and intelligent innovation.

As a global leader in information and communications technology (ICT), Huawei drives innovation in artificial intelligence, cloud computing, and smart device technologies. Through its Carrier, Enterprise, and Consumer business groups, the company delivers advanced Network Infrastructure, Cloud and AI Platforms, and industry‑leading devices.

Huawei supports 45 of the world’s top 50 telecom operators and serves one‑third of the global population, with operations in over 170 countries and a workforce of more than 200,000 employees.

Huawei Technologies Switzerland AG contributes to this innovation through cutting‑edge research, with offices in Zurich and Lausanne focusing on High‑Performance Computing, Computer Architecture, Computer Vision, Robotics, Artificial Intelligence, Neuromorphic Computing, Wireless Technologies, Networking, and related fields.

We are a unique team of innovative, diverse individuals who have come together from multiple backgrounds to create advanced Computing Architectures for communication systems/Edge AI. The people who work here are generalists, and we complement each other. The passion for exploring uncharted territory makes us thrive.

We seek a highly talented (Senior) researcher with research experience in the field of computing architecture. If you have technical research experience in areas such as AI computing, SoC architecture, heterogeneous systems, cores, and buses, particularly with expertise in chip optimization for high performance, low latency, and low power consumption, this is an excellent opportunity for you.

• Identify technology trends in Edge AI, scalar/vector/tensor processing, and CPU/GPU/NPU/TPU microarchitecture optimization techniques.
• Propose novel technologies in computing architecture, memory/cache, interconnect and/or SoC design in general to improve Performance, Power efficiency and Area efficiency (PPA), system flexibility, etc.
• Develop novel computing architecture to improve the performance and efficiency of chip systems through software‑hardware co‑design and other technical innovations.
• Develop and maintain long‑term strategic partnerships with the industry and academia from leading universities, and collaborate with professors specializing in computer architecture.

• MSc or PhD in computer science, electrical engineering, wireless communication or related background.
• At least 5 years of work experience in chip‑related fields.
• A strong background in hardware‑software co‑design, microprocessor architecture for scalar/vector/tensor computing, job scheduling in heterogeneous parallel systems, memory optimization in many‑core systems, power optimization, etc.
• Candidates with experience in AI chip design and power & area efficiency optimization are preferred.
• Candidates with a good understanding of hardware‑software interfaces and interactions, and experience in compiler technology, are preferred.
• Excellent communication skills across organizations and at the executive level.
• Fluency in English, both written and verbal. Chinese is a plus.
• Excellent written skills for clear and concise reporting.

• Collaborate with world‑class scientists and engineers in an open, curiosity‑driven environment.
• Access to state‑of‑the‑art technology and tools.
• Opportunities for professional growth and development.
• Competitive salary, and a high quality of life in Zurich, at the center of Europe.
• Last but certainly not least: be part of innovative projects that make a difference.

• Work location: 8600 Dübendorf (ZH)
• Workload: 100%
• Employment start: Immediately
• Employment duration: Permanent
• Qualification: skilled
• Work experience: More than 1 year
• Education: Master’s degree from a university or equivalent
• English (spoken): Very good knowledge
• English (written): Very good knowledge
• Application method: Online form