Memory Verification Engineer - SystemVerilog​/UVM

Renesas is seeking an experienced Staff Design Verification Engineer to join our team focused on memory interface products for data center, AI, and cloud computing applications. You will verify advanced memory data buffer products, including DDR6 and future generations, using System Verilog/UVM environments and test benches.

Ideal candidates bring 8+ years in semiconductor design verification, strong System Verilog/UVM expertise, and a track record of owning complex verification assignments from

This opportunity is for the Staff Memory Verification Engineer
- System Verilog/UVM role at Renesas Electronics Corp.

Join Renesas Electronics Corp. and contribute to our ongoing work.

Take a moment to read everything above and see whether this role is right for you.

This posting is for the Staff Memory Verification Engineer
- System Verilog/UVM role at Renesas Electronics Corp., based in Duluth, GA, United States.