Senior ASIC Design Engineer - Hybrid Networking Chips
Listed on 2026-10-12
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Engineering
Systems Engineer, Hardware Engineer
Hewlett Packard Enterprise Development LP seeks a Senior ASIC Design Engineer for its Durham, NC Silicon group. The role is hybrid, with in-office presence 2 days per week and US citizenship preferred.
You will architect modules for high-performance networking chips, write specs, and implement in Verilog/System Verilog while collaborating with physical design, verification, and power teams. Mentoring interns and new grads is also expected.
The Senior ASIC Design Engineer
- Hybrid Networking Chips position in the IT & Technology, Engineering field is open for applications.
We aim to respond to suitable candidates as soon as possible.
Full responsibilities and requirements are described in the listing above.
Learn more about the Senior ASIC Design Engineer
- Hybrid Networking Chips role in the description above.
We appreciate your interest in this position.
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