ASIC Verification Engineer

* 4+ years of experience in ASIC/SoC verification with a proven track record of owning verification from test plan to coverage closure.
* Strong expertise in System Verilog and UVM methodology, including developing environments from scratch.
* Deep understanding of randomization, constraints, functional coverage, and assertions (SVA).
* Hands-on experience in test planning, coverage analysis, and debugging of complex SoC designs.
* Proficiency with industry-standard simulation tools (e.g., Cadence Xcelium, Synopsys VCS, Mentor Questa) and waveform debugging.
* Experience verifying networking ASICs or router datapath/control blocks, such as packet processing, forwarding engines, or fabric interfaces.
* Familiarity with high-speed interconnects, buffers, or scheduling pipelines in large networking SoCs.
* Exposure to emulation environments, hardware acceleration, or traffic-model integration.
* Knowledge of coverage analytics, regression dashboards, and continuous-integration flows (e.g., Jenkins).
* Understanding of low-power (UPF) or formal verification methodologies.
* Own and drive block-level/subsystem/Full Chip verification efforts, from creating test plans to achieving comprehensive coverage closure
* Experience with post-silicon bring-up and debug is a plus.
* Familiarity with emulation environments and debug flows is desirable.

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