Senior Verification Engineer — AI-Driven UVM & ML

Base salary + RSUs + Bonus + Emloyee stock purchase scheme

I am working with a world-class engineering team based in Edinburgh, developing leading-edge IP for a wide range of high-tech markets. They are looking for a Senior Design Verification Engineer. As part of the Engineering group, you will play a key role in defining and driving the adoption of advanced verification tools and methodologies, with a particular focus on AI and machine learning.

This is a cross-functional role, collaborating with multiple projects and teams to accelerate the adoption of best-in-class verification practices.

• Develop and support the adoption of generative AI tools to create and maintain UVM and formal verification environments
• Define methodologies and end-to-end flows to ensure AI tools are used in a consistent, efficient, and predictable manner
• Develop and deploy solutions to reduce verification debug time
• Automate documentation checks to improve quality and consistency
• Build tools and processes to support verification planning
• Optimise UVM regression flows through enhanced automation and machine learning techniques
• Maintain and evolve best practices for Functional Safety Verification, Gate-Level Simulation, and Low Power Verification

• Degree in Electrical/Electronic Engineering, Microelectronics, or a related discipline
• 4+ years’ experience in the microelectronics/EDA industry
• Proficiency in System Verilog and assertions
• Hands‑on experience with metric‑driven verification
• Strong knowledge of constrained‑random verification techniques (e.g. UVM)
• Experience with formal verification
• Proficiency in scripting languages such as Python
• Knowledge of AI agent development

As a leading semiconductor company, you can expect a highly competitive compensation package, including salary, RSUs, a bonus scheme, and an employee stock purchase plan. Additional benefits include wellness days, as well as private medical and dental coverage.