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Senior Principal Design Engineer: Chiplet IP & RTL Leader
Job in
City of Edinburgh, Edinburgh, City of Edinburgh Area, EH1, Scotland, UK
Listed on 2026-07-19
Listing for:
Cadence
Full Time
position Listed on 2026-07-19
Job specializations:
-
Engineering
Systems Engineer
Job Description & How to Apply Below
Cadence Edinburgh is seeking a Sr Principal Design Engineer to lead complex silicon programs and drive frontend design activities within a seasoned team. You will collaborate with Chiplet Architecture to define next‑generation Chiplets and oversee the integration of Cadence IP and partner IP across PCIe, UCIe, and related interfaces.
You will lead RTL, testbench, formal analysis and verification efforts, ensuring high‑quality deliverables and adherence to ISO‑9001 processes, while engaging with
#J-18808-LjbffrPosition Requirements
10+ Years
work experience
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