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Hybrid Design Verification Engineer (SystemVerilog​/UVM

Job in City of Edinburgh, Edinburgh, City of Edinburgh Area, EH1, Scotland, UK
Listing for: IC Resources
Full Time position
Listed on 2026-08-15
Job specializations:
  • Engineering
    Test Engineer
Salary/Wage Range or Industry Benchmark: 55000 - 85000 GBP Yearly GBP 55000.00 85000.00 YEAR
Job Description & How to Apply Below
Position: Hybrid Design Verification Engineer (SystemVerilog/UVM)
Location: City of Edinburgh

IC Resources has an opportunity for Design Verification Engineers to join a leading UK semiconductor engineering team. You’ll work on ASIC/SoC verification life cycles, owning the verification of complex digital subsystems and mixed-signal ICs.

Positions open at multiple levels from engineer to senior/principal, with hybrid work in Edinburgh or Newbury and a strong engineering culture.

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