Principal Design Engineer

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world's most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Job Title:

Principal Digital Implementation Engineer

Location:

Munich, Cork, Katowice, Edinburgh

Reports to:

Senior Principal Engineer

The Role:

We are seeking an exceptional Principal Digital Design Engineer to join the Performance Solutions Group (PSG). The candidate will contribute to the development of complex, high-performance semiconductor designs. You will work as part of a multidisciplinary engineering team, developing and integrating RTL for advanced SoCs and silicon platforms. You will be involved throughout the front-end design process, from understanding architectural requirements and developing microarchitectures through RTL implementation, simulation, synthesis, and handoff to downstream teams.

This is a hands-on engineering role suited to someone who enjoys solving challenging technical problems, learning new technologies, and working across the boundaries between architecture, RTL, verification, and physical implementation.

• Design, implement, and integrate high-quality synthesizable RTL using System Verilog.
• Translate architectural specifications into robust, efficient microarchitectures and RTL implementations.
• Work with architects and senior engineers to understand functional and performance requirements.
• Develop RTL that meets requirements for performance, power, area, and functionality.
• Participate in RTL design reviews and contribute to design methodology and coding standards.
• Develop and maintain unit-level and block-level test environments in collaboration with verification engineers.
• Debug functional issues using simulation, waveform analysis, assertions, and other verification tools.
• Work with verification teams to identify, reproduce, and resolve RTL design issues.
• Collaborate with physical design engineers to understand and address timing, area, power, and implementation constraints.
• Support synthesis, timing analysis, linting, CDC analysis, and other front-end quality checks.
• Contribute to integration of internally developed and third-party IP.
• Help investigate and resolve issues encountered during integration and downstream implementation.
• Document design decisions, interfaces, microarchitecture, implementation details and reviews within the PSG Quality Management System (QMS).
• Contribute to continuous improvement of RTL methodologies, automation, and development flows.
• Work alongside senior engineers to develop solutions to challenging customer and internal silicon problems.

• System Verilog RTL SoC and subsystem design
• CPU, GPU, AI/ML, networking, or other high-performance compute architectures
• Control logic and datapaths
• Memory interfaces and controllers
• High-speed interfaces
• Clock and reset architectures
• AMBA protocols such as AXI, AHB, and APB
• IP integration
• Low-power design techniques
• Assertions and formal verification
• RTL synthesis and optimization
• Static analysis, lint, and CDC
• Performance and power optimization
• RTL-to-gates implementation flows

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related discipline.
• 10+ years of relevant RTL/ASIC design experience.
• Proficiency in Verilog or System Verilog.
• Understanding of digital logic design and synchronous design principles.
• Experience developing synthesizable RTL for ASIC or FPGA implementations.
• Familiarity with simulation and RTL debugging.
• Understanding of common SoC interfaces and protocols.
• Basic understanding of synthesis, timing, and physical implementation considerations.
• Ability to analyze complex technical problems and develop practical solutions.
• Strong written and verbal communication skills.
• Ability to work effectively within a multidisciplinary engineering team.
• Ability to communicate effectively to customers.

Deliver robust RTL. Develop clean, maintainable, synthesizable RTL that meets functional and performance requirements. Think beyond the RTL. Understand how design decisions affect verification, synthesis, timing, power, area, and ultimately silicon. Solve problems independently. Take ownership of assigned blocks and issues while knowing when to seek guidance from more senior engineers. Work collaboratively. Build strong working relationships with architects, verification,…