Principal Digital RTL Engineer — SoC & Silicon Impact
Listed on 2026-10-11
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Engineering
Hardware Engineer, Systems Engineer, Electronics Engineer, Test Engineer
Cadence Design Systems in Edinburgh, UK, seeks a Principal Digital Design Engineer to drive high-performance RTL development for advanced SoCs within the PSG. You will own RTL from architectural concepts through synthesis and handoff, collaborating with architecture, verification, and physical design teams to solve complex silicon problems.
The role targets senior engineers with expertise in System Verilog, RTL debugging, and timing closure, contributing to cutting-edge semiconductor solutions
This is a strong role to take on the Principal Digital RTL Engineer — SoC & Silicon Impact role at Cadence Design Systems.
The Principal Digital RTL Engineer — SoC & Silicon Impact position in the Engineering field is open for applications.
We have an opening for a Principal Digital RTL Engineer — SoC & Silicon Impact in City of Edinburgh, Scotland, United Kingdom within Engineering.
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