SoC Physical Verification Lead - Tapeout Signoff
Listed on 2026-11-04
-
Engineering
Hardware Engineer, Test Engineer, Electronics Engineer
Deel is seeking an experienced SoC Physical Verification Engineer in the United Kingdom to lead full-chip and hierarchical signoff, including DRC, LVS, ERC, PERC, and DFM. You will work with PD, CAD, RTL, and EDA vendors to ensure tapeout-ready silicon and robust reliability across next-generation designs.
The role requires hands-on leadership, strong debugging, and scripting skills, with experience in advanced nodes and memory-centric SoCs.
This posting is for the SoC Physical Verification Lead
- Tapeout Signoff role at Deel, based in United Kingdom.
Full responsibilities and requirements are described in the listing above.
Learn more about the SoC Physical Verification Lead
- Tapeout Signoff role in the description above.
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