Experienced Design Verification Engineer San Jose

Join eInfochips as a Design Verification Engineer in San Jose, CA. Bring your expertise in System Verilog and UVM to enhance verification processes for cutting-edge technologies.

With over 6 years of experience required, this position demands proficiency in System Verilog HVL and C++/C, alongside solid UVM knowledge. You'll manage the complete verification cycle, developing test plans, debugging, and ensuring coverage closure. Ideal candidates should also be familiar with scripting languages like Make, Perl, or Python, contributing to customer satisfaction through effective progress reporting.

Key Responsibilities:

• Develop test plans and manage BFM/Driver/Monitor components

• Perform stress testing and debugging for verification closure

• Conduct gate-level simulations and assertions coding

• Handle Subversion and Bugzilla for repository management

• Ensure customer satisfaction through effective reporting

Requirements:

• 6+ years of experience in System Verilog and C++/C

• 6+ years in UVM with strong scripting skills

• Any protocol experience is beneficial

• Understanding of DSP preferred

• Willingness to travel as needed

Elevate your engineering career by applying your verification skills with eInfochips in San Jose.
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