Senior FPGA Design & Verification Engineer - Wireless

KRUSHLabs in Eindhoven is seeking an experienced FPGA Design and Verification Engineer to join their team working on advanced wireless communication systems. The engineer will create and maintain design and verification flows, utilizing expertise in System Verilog, C/C++, and Python. Key responsibilities include developing RTL modules, integrating IP blocks, and supporting FPGA methodologies. A Master's degree in Electronic Communication Systems and experience in VLSI design/verification are essential.

Join us to shape the future of communication technology.
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