Senior Modem SOC Design Engineer - TeraWave

At Blue Origin, we envision millions of people living and working in space for the benefit of Earth. We’re working to develop reusable, safe, and low-cost space vehicles and systems within a culture of safety, collaboration, and inclusion. Join our team of problem solvers as we add new chapters to the history of spaceflight! Blue Origin is pioneering the future of space-based connectivity with Tera Wave, a revolutionary satellite communications network designed to deliver symmetrical data speeds of up to 6 Tbps anywhere on Earth.

This network will service tens of thousands of enterprise, data center, and government users who require reliable connectivity for critical operations.

As a Senior Modem SOC Design Engineer on the ASIC Engineering SOC Team, you will design digital hardware for the Tera Wave satellite communication System on Chip (SOC). You will own RTL design for modem datapath and PHY blocks, implement signal processing hardware, and build out the Arm compute subsystem, debug, and IO infrastructure that surround it. This is an individual contributor role with no direct reports.

You will work from communication system specifications through microarchitecture, RTL, SOC integration, and timing closure, partnering with architecture, verification, and physical design teams to deliver production silicon.

• Design RTL in Verilog or System Verilog for modem datapath and PHY blocks
• Define microarchitecture from satellite communication system specifications and performance requirements
• Implement signal processing hardware including filters, FFT, equalizers, and forward error correction
• Develop Arm compute subsystem logic including AXI interconnect and SRAM controller integration
• Integrate debug subsystem components using Arm Core Sight architecture and associated trace infrastructure
• Design general purpose IO subsystem logic and associated configuration register interfaces
• Integrate subsystem and SOC level blocks including clock and reset architecture
• Support synthesis, timing constraint development, and timing closure with physical design teams

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related technical field
• Minimum 5 years of experience in digital ASIC or SOC RTL design
• Experience with RTL design in Verilog or System Verilog for modem or PHY blocks
• Experience with Arm compute subsystem design including AXI interconnect and SRAM controllers
• Experience implementing signal processing hardware such as filters, FFT, or forward error correction

• Master's degree in Electrical Engineering, Computer Engineering, or related technical field
• Experience with debug subsystem design using Arm Core Sight components
• Experience defining microarchitecture from communication system and algorithm specifications
• Experience with SOC level integration including bus fabric, clock, and reset architecture
• Experience with synthesis, timing constraint development, and timing closure support
• Experience with LPDDR6 or other high speed memory interface subsystems
• Experience with gigabit Ethernet or 25G high speed serial interface subsystems

Base Pay Range for: CA applicants is $ - $ WA applicants is $ - $ Other site ranges may differ

Don’t meet all desired requirements? Studies have shown that some people are less likely to apply to jobs unless they meet every single desired qualification. At Blue Origin, we are dedicated to building an authentic workplace, so if you’re excited about this role but your past experience doesn’t align perfectly with every desired qualification in the job description, we encourage you to apply anyway.

You may be just the right candidate for this or other roles.

Applicants…