FPGA Design Verification Engineer

We are currently hiring for an FPGA Design Verification Engineer for an opportunity based in El Segundo, California.

FPGA Design Verification Engineer

El Segundo, CA

5+ years

U.S. Citizens only

Secret DoD clearance preferred

We are looking for an experienced FPGA Design Verification Engineer with hands-on expertise in System Verilog, UVM, and verification testbench development. The ideal candidate will have experience developing verification plans, building reusable verification components, analyzing functional coverage, and supporting FPGA verification activities throughout the development lifecycle.

• Develop and maintain System Verilog and UVM-based verification test benches.
• Create and execute verification plans, test scenarios, and functional tests.
• Develop reusable verification components and verification IP.
• Perform functional coverage analysis and drive coverage closure.
• Develop C-based tests and support hardware/software integration.
• Debug simulation failures and work with design teams to resolve verification issues.
• Support FPGA verification from initial planning through final verification sign-off.
• Collaborate with hardware, firmware, and system engineering teams.

• At least 5 years of hands-on FPGA design verification experience.
• Strong knowledge of System Verilog and UVM.
• Experience with testbench development and verification planning.
• Functional coverage analysis and coverage closure.
• Experience developing reusable verification components.
• C/C++ test development or hardware/software integration experience.
• Ability to work independently and troubleshoot technical issues.

• Space Wire protocol
• DDR4 memory interfaces
• Ser Des connectivity
• Configuration, control, and telemetry systems
• Aerospace or defense-related systems
• Active Secret DoD security clearance

Please note that U.S. citizenship is mandatory for this position. A Secret DoD clearance is preferred.