Senior Clocking Architect — Ultra-Low Jitter SerDes
Listed on 2026-11-05
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Engineering
Hardware Engineer -
Design & Architecture
Upscale, Inc. is building the next generation of AI infrastructure and is seeking a senior clocking architecture leader for Ser Des design.
You will define PLLs, clock generation, and distribution for 5nm and below processes, collaborating across analog, digital, layout, and silicon validation teams to achieve extreme timing performance. You will drive architectural innovation, tackle jitter and power-efficiency challenges, and deliver silicon-ready clocking solutions for 100G+ Ser Des in a
We invite applications for the Senior Clocking Architect — Ultra-Low Jitter Ser Des position located in KY, United States.
We would love to welcome a new Senior Clocking Architect — Ultra-Low Jitter Ser Des to our team in KY, United States.
For the Senior Clocking Architect — Ultra-Low Jitter Ser Des position at Upscale, we are reviewing applications now.
Step into the Senior Clocking Architect — Ultra-Low Jitter Ser Des role at Upscale in KY, United States and grow with us.
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