Senior Software Engineer

Overview

Senior Software Engineer for Edge AI Applications. UBIETY Technologies Ltd requires a senior software engineer to develop the software stack for industrial Edge AI devices such as multiphase flow meters and medical imaging instruments. Each instrument couples an analogue front end with an AMD Zynq Ultra Scale+ MPSoC. The role works alongside an FPGA specialist, who owns the programmable logic for deterministic timing, acquisition and high-rate data movement, and a Signal Processing and Tomography engineer, who develops the reconstruction and flow algorithms in MATLAB and Python.

The software engineer owns the processing system side of the PS–PL boundary: register maps, DMA buffers, interrupts, device tree, embedded Linux services for control, processing, diagnostics, industrial communication and user interaction, and the backend processing and user-facing interfaces. A central task is to translate the MATLAB/Python reference algorithms onto the PS — and, with the FPGA specialist, onto the PL — covering acquisition orchestration, waveform capture, diagnostic extraction, path health checks, flow-computation support and data persistence.

The three roles operate as a single team, and broader cross-disciplinary collaboration is expected and valued.

• Area Expected ownership
• Embedded Linux
• Board software, Linux application services, boot/runtime configuration, logging, watchdogs and deployment
• AXI-Lite control, AXI DMA integration, DDR buffer management, interrupt handling, packet formats, deserialisation boundaries and PL bring-up tools
• Acquisition orchestration, waveform capture, diagnostic extraction, path health checks, flow-computation support and data persistence
• Ethernet services, Modbus TCP register map, process-variable publishing, alarm/status words and configuration access
• Audit trail, protected calibration parameters, version traceability, configuration CRC, role-based access and controlled update/rollback
• Backend processing
• Custody-transfer integrity

• Skill group:
  Embedded Linux;
  Yocto or Peta Linux, U-Boot, kernel/device-tree awareness, systemd, cross-compilation, network configuration and field update strategy
• Modern C++ and C for low-level interfaces, multithreading, bounded queues, binary protocol handling, error handling, performance profiling and CMake/Make
• AXI-Lite, AXI-Stream, AXI DMA/CDMA, memory-mapped I/O, UIO/VFIO or kernel drivers, interrupts, cache coherency, contiguous buffers, serial-link bring-up and deserialised packet validation
• Clipping, gain and path diagnostics; translating MATLAB/Python reference algorithms into efficient, validated embedded C/C++
• On-device inference of trained models on the MPSoC:
  Vitis AI/DPU or equivalent runtimes, ONNX import, model quantisation and optimisation, fixed-point/integer pipelines and PS–PL partitioning of the inference workload
• Modbus TCP, TCP/IP sockets, REST/Web Socket APIs, register scaling, engineering units, endian handling and alarm/status design
• Type Script with React/Vue/Svelte or equivalent, real-time charts, configuration screens, service pages, role-based access and waveform snapshots
• Git, issue tracking, test automation, reproducible builds, logging, fault injection, diagnostics and release documentation
• Signal processing & algorithm porting
• Communications
• UI implementation
• Quality discipline
• AMD Zynq Ultra Scale+ MPSoC, industrial instrumentation, test-and-measurement systems
• Tomographic reconstruction or medical/industrial imaging pipelines (ultrasound, MRI, CT) and hardware-aware optimisation of ML inference
• Interest or experience in SciML such as PINNs/PIML is a distinct advantage but not mandatory
• Custody-transfer, legal-metrology, auditability, calibration locking, tamper evidence and secure device service access
• OPC UA, MQTT, TLS/certificates, signed updates, A/B root file system deployment and factory-test automation