Substrate Layout Engineer
Listed on 2026-10-12
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Engineering
Electronics Engineer, Electrical Engineering, Manufacturing Engineer, Hardware Engineer
Piper Companies is seeking a Substrate Layout Engineer to join a rapidly growing AI infrastructure and semiconductor technology organization. The Substrate Layout Engineer will support the physical layout and routing of advanced organic substrates, interposers, and package technologies for next-generation multi-die compute products designed for high-performance AI and data center applications.
The Substrate Layout Engineer requires you to work onsite 5 days per week in Sarasota, CA.
Responsibilities of the Substrate Layout Engineer:- Perform physical layout of organic substrates and interposers, including die placement, bump-map alignment, netlist implementation, escape routing, signal routing, power routing, reference planes, via structures, and stack-up implementation.
- Develop routing solutions for high-speed interfaces and high-current power delivery networks.
- Support routing feasibility studies and collaborate with package integration, ASIC, signal integrity, power integrity, and mechanical engineering teams.
- Apply and maintain layout constraints while coordinating design reviews with cross-functional stakeholders.
- Perform connectivity verification, DRC, DFM, and manufacturing rule checks.
- Prepare release databases, design documentation, and manufacturing deliverables.
- Work directly with substrate suppliers, fabrication partners, and manufacturing teams to resolve design and manufacturability challenges.
- Support package interface board layout activities and contribute to process improvements and best practices.
- 8+ years of hands-on experience with substrate, package, interposer, or complex multilayer PCB layout design.
- Experience with Siemens Xpedition, Cadence Allegro, or comparable package and PCB layout tools.
- Strong knowledge of high-density routing, bump escape techniques, via structures, and stack-up implementation.
- Working understanding of high-speed signal routing and/or power delivery network design.
- Experience performing connectivity checks, design rule checks (DRC), design for manufacturability (DFM), and manufacturing release procedures.
- Ability to collaborate effectively with engineering teams, suppliers, and manufacturing partners.
- Experience supporting multi-die, chiplet-based, or advanced package designs is highly preferred.
- Bachelor's degree in Engineering or equivalent combination of education and relevant industry experience.
- Salary range: $180,000 - $270,000 base salary
- Full Comprehensive Benefits:
Health, Vision, Dental, PTO, Paid Holiday and Sick Leave if Required by Law.
Substrate Layout Engineer, Package Layout Engineer, Organic Substrates, Interposer Design, Multi-Die Packaging, Chiplet Architecture, Advanced Packaging, High-Speed Routing, Power Delivery Networks, PDN, Signal Integrity, Power Integrity, Bump Escape Routing, Siemens Xpedition, Cadence Allegro, Package Design, PCB Layout, High-Density Routing, DRC, DFM, Manufacturing Release, IC Packaging, Semiconductor Engineering, AI Infrastructure, Data Center Hardware, Package Integration, Advanced Semiconductor Packaging, Electrical Design, Stack-Up Design, Via Structures, ASIC Packaging
This job opens for applications on 10/09/2026. Applications for this job will be accepted for at least 30 days from the posting date.
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