Speed I​/O PHY Architect

Join to apply for the High-Speed I/O PHY Architect role at Intel Corporation
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Join Our Team as a High-Speed I/O PHY Architect.

Are you a visionary in High-Speed I/O PHY Architecture? Do you have a passion for driving innovation and shaping the future of cutting‑edge PHYs for next‑generation client SoCs? If so, we want you to be a part of our Client CIT team. In this pivotal role, you will be instrumental in defining the architecture, performance, and power efficiency of our high‑speed interfaces, directly impacting the success of our client products.

Collaborate closely with a diverse range of cross‑functional teams to ensure seamless integration and optimized system‑level performance. This is a high‑impact role offering the opportunity to drive innovation and influence the future of our client SoC technology.

• Architectural Leadership:
  Lead the architectural definition and integration of high‑speed PHYs for client SoCs, including PCIe, CXL, USBx (eUSB2, USB3, USB4), Display, MIPI (D‑PHY, C‑PHY, M‑PHY), Ethernet, and TSN. Collaborate with platform and product architects to analyze requirements and define critical performance, power, and area specifications to ensure the success of our products.
• IP Evaluation:
  Conduct technical evaluations of both internal and external PHY IPs, analyze their performance characteristics against product requirements, and ensure strategic alignment with overall product goals. Define detailed IP requirements, lead vendor engagement, and make strategic IP selection recommendations based on technical feasibility, cost‑effectiveness, and long‑term roadmap alignment.
• Technology Vision:
  Proactively research and evaluate emerging high‑speed I/O technologies, industry trends, and evolving standards. Identify and champion opportunities to incorporate these advancements into our product roadmap, enhancing performance, power efficiency, and feature sets, and positioning our products for competitive advantage.
• Technical Documentation:
  Create clear and comprehensive architecture specifications and rigorous integration guidelines. Provide review and constructive feedback on related architectural specifications to ensure alignment with overall SoC goals.
• Technical Mentorship and
  
  Collaboration:
  
  Provide technical guidance and mentoring to junior engineers, fostering their growth and contributing to the overall team expertise. Champion a collaborative environment across multiple teams.
• Post‑Silicon Leadership:
  Serve as a technical lead in the post‑silicon debug and validation of high‑speed I/O interfaces, leading taskforces and driving the resolution of complex issues. Oversee the validation process to ensure seamless and high‑quality implementations.

• Demonstrated strategic acumen with proven effectiveness in collaborating with senior technologists and business leaders across organizational boundaries.
• Demonstrated ability to network with and influence a broad range of stakeholders.

• BS degree in Electrical/Computer Engineering with a minimum of 15 years of experience.
• Master’s or PhD degree in Electrical/Computer Engineering with minimum 12 years of experience.

• High familiarity with industry trends within the HSIO domain and the ability to map them to Intel roadmap/products and segment strategies.
• Prior hands‑on experience in High‑Speed I/O PHY Architecture and Design.
• Strong knowledge in the interoperability of HSIO PHYs within the PCIe, SATA, Ethernet, USB2, USB3, USB4, Display or MIPI I/O Controller subsystems.
• Strong technical leadership and communication skills.
• We look forward to welcoming a dynamic and innovative High‑Speed I/O (PHY) Architect to our team. Apply now and be a part of shaping the future of our client SoC technology.

Experienced Hire

Shift 1 (United States of America)

US, California, Folsom

US, Arizona, Phoenix; US, California, Santa Clara; US, Oregon, Hillsboro

The Silicon Engineering Group (SIG) is a worldwide organization focused on the development and integration of SOCs, cores, and critical IPs from architecture to…