AI Frameworks Architect

AI Frameworks Architect – Intel Corporation

Join to apply for the AI Frameworks Architect role at Intel Corporation
.

The Intel NPU IP Architecture team is looking for an AI Frameworks Architect to lead VPU architecture performance modeling and analysis activities.

In this position, you will function as a senior technical member in the NPU architecture performance COE team. The primary responsibility of the team includes developing the next generation NPU architecture performance model and conducting performance analysis using models from various benchmarking suites or customer end‑to‑end use cases.

• Define performance model architecture and modeling flow to best reflect the interworking of NPU SW/HW.
• Implement and test performance models with systematic software development practice.
• Conduct performance‑and‑power analysis of various neural network workloads.
• Utilize the performance data‑driven flow to drive the NPU architecture definition.
• Collaborate with management, product owners, and project managers to evaluate feasibility of requirements and determine priorities for development.
• Perform pathfinding, survey technologies, participate in standards committees, and present at external and internal events.
• Interact with multiple technologists in the company to influence architectures and optimize/customize software offerings.

You must possess the minimum education requirements and qualifications to be initially considered for this position. Additional preferred qualifications are considered a plus.

• Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field with 6+ years of relevant experience; or Master’s Degree with 4+ years; or PhD with 2+ years (or equivalent).
• 6+ years of experience in two or more of the following:
  • Computer architecture concepts such as pipelining, caching, parallel computing with SIMD/VLIW, multi‑core/multi‑threading, data precision, memory hierarchy.
  • Hardware modeling concepts such as event‑driven, concurrency, etc.
  • AI frameworks, AI models, and basic neural computing operations.
  • Data precision, floating point vs fixed point computing trade‑offs.

• Experience with object‑oriented programming in C/C++ or Python, capable of designing class objects, data structures, and API methods.
• Prior usage of event‑driven modeling language (System
  
  C/C++/Python) and platforms.
• Prior experience in architecture definition and/or mentoring junior engineers.

Experienced Hire.

Shift 1 (United States of America).

U.S., California, Santa Clara.

U.S., Arizona, Phoenix; U.S., California, Folsom; U.S., Oregon, Hillsboro; U.S., Oregon, Portland.

The Silicon Engineering Group (SIG) is a worldwide organization focused on the development and integration of SOCs, cores, and critical IPs from architecture to manufacturing readiness that power Intel’s leadership products.

All qualified applicants will receive consideration for employment without regard to race, color, religion, creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

We offer a total compensation package that ranks among the best in the industry, including competitive pay, stock, bonuses, and benefits programs such as health, retirement, and vacation. The annual salary range in the U.S. is $–$ USD.

This role requires an on‑site presence. Posting details are subject to change.