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GPU Logic Design Engineer

Job in Folsom, Sacramento County, California, 95630, USA
Listing for: Intel
Full Time position
Listed on 2025-12-09
Job specializations:
  • Engineering
    Systems Engineer, Software Engineer
Salary/Wage Range or Industry Benchmark: 80000 - 100000 USD Yearly USD 80000.00 100000.00 YEAR
Job Description & How to Apply Below
Job Details:

Job Description :
  • RTL design for 3D Graphics Fixed Function components. Develops the logic design, register transfer level (RTL) coding, and simulation for graphics IPs (including graphics, compute, display, and media) required to generate cell libraries, functional units, and the GPU IP block for integration in full chip designs.

  • Participates in the definition of architecture and microarchitecture features of the block being designed.

  • Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation.

  • Reviews the verification plan and implementation to ensure design features are verified correctly across verification hierarchies, drives unit level verification, and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.

  • Supports SoC customers to ensure high-quality integration of the GPU block.

Qualifications:

Minimum Qualifications

  • Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field with 3+ years of industry experience OR

  • Master's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field with 2+ years of industry experience.

Preferred Qualifications

  • Experience in System Verilog/C++/OVM or UVM methodology and/or Formal Verification techniques.

  • Experience in RTL logic design using System Verilog and RTL development design partitioning microarchitecture tradeoffs and high-speed digital logic design including timing closure.

  • Experience in System simulation models and debugging RTL/tests with cross-site teams.

  • Experience in working with validation engineers to develop functional validation and coverage test plans.

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary

Location:

US, California, Folsom

Additional Locations:

US, Oregon, Hillsboro

Business group:

The Data Center & Artificial Intelligence Group (DCAI) is at the heart of Intel’s transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies—spanning software, processors, storage, I/O, and networking solutions—that fuel cloud, communications, enterprise, and government data centers around the world.

Posting

Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Benefits:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US:

$-$

Salary range dependent on a number of factors including location and experience.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.
* Job posting details (such as work model, location or time type) are subject to change.

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