Methodology Lead

Job Details

In this position, the candidate will be part of a team implementing Integrated/Discrete Graphics blocks and AI SoCs on leading edge process technologies and EDA tools. The team is responsible for all SoC level physical design and optimization flows ranging from floor planning, synthesis through GDS and parallel verification aspects such as static timing analysis, formal verification, EM/IR/PDN aspects, layout verification, etc.

The candidate would be required to work closely with the rest of the project team members to resolve issues which arise during the design cycle and take the key learnings into the next product cycle. Good interpersonal/communication skills are necessary due to the nature of work, size/complexity of products and the size of the team.

A successful candidate will have proven experience demonstrating the following skills and behavioral traits:

• Will have the skills and experience to lead APR methodology development and deployment for a product team.
• This includes understanding leading edge vendor capabilities and how to quickly deploy to a large execution team.
• The candidate must balance new capabilities, user requirements, environment stability and product needs/timelines to seamlessly deploy and support APR methodologies.

Minimum qualifications are required to be initially considered for this position.

• Bachelor's in Electrical/Computer Engineering with 10+ years relevant work experience, or Master's in Electrical/Computer Engineering with 8+ years relevant work experience.
• 10+ years of hands‑on experience with industry standard tools in VLSI/ASIC design.
• Relevant coursework/experience should include:
  • Advanced Logic Design/VLSI/ASIC Design/Computer Architecture.
  • Advanced knowledge of common ASIC style design flows – floor planning, synthesis, place/route, layout verification, static timing analysis, formal/layout verification.
  • Advanced knowledge of SoC hierarchical design and integration with experience in floorplan/timing integration of a variety of APR sub‑blocks.
  • Basic knowledge and experience with Unix/Linux, Perl and TCL to implement usable, flexible cShell/perl/tcl programs that automate tool/flow methodologies.

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual salary range for jobs which could be performed in the US: $– USD. The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job‑related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

This role will be eligible for our hybrid work model which allows employees to split their time between working on‑site at their assigned Intel site and off‑site. Job posting details (such as work model, location or time type) are subject to change.

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.