CPU Core Physical Design Technical Graduate Intern

** Welcome!**.CPU Core Physical Design Technical Graduate Intern, Spring page is loaded## CPU Core Physical Design Technical Graduate Intern, Spring locations: US, California, Folsom time type:
Full time posted on:
Posted Todayjob requisition #
** Job Details:**##

Job Description:

** The Role and Impact
** As a 2027 Physical Design Engineering Graduate Intern, you will contribute to the physical implementation of silicon designs to create manufacturing-ready solutions. Your day-to-day work will involve tasks such as synthesis, place and route, timing analysis, clocking, and/or integration. By assisting in verification and signoff activities, you will ensure manufacturability and performance compliance, directly supporting Intel's broader innovation goals.
** Business group
** The Data Center Group (DCG) is at the forefront of transforming data-centric technologies by delivering solutions that power Intel's silicon and platform advancements. Focused on high-performance computing, storage, and connectivity, DCG plays a vital role in shaping Intel's impact across industries, enabling scalable, automated, and impactful designs for modern infrastructure challenges.
** January 2027 - August 2027
**** Ideal candidate is local to Folsom area or will arrange for a semester away.
**** Relocation is available.
**** Key Responsibilities**- Support physical design implementation, including synthesis, place and route, and integration.

- Conduct timing analysis and clocking to optimize design performance.

- Assist in verification and signoff activities to ensure manufacturability and compliance.

- Collaborate with cross-functional teams to enhance design scalability and automation.

- Learn and apply knowledge through hands-on tasks and projects aligned with Intel's goals.##
*
* Qualifications:

**** Minimum Qualifications
*** Pursuing a Master's degree in Electrical Engineering (EE), Computer Engineering (CE), or a related field.
* Coursework, academic projects, or research experience in digital integrated circuit design and VLSI physical design.
* Fundamental knowledge of logic synthesis, place and route, and static timing analysis (STA).
* Experience with one or more scripting/programming languages such as Perl, Tcl, or Python.
* Understanding of semiconductor design flows and ASIC/SoC implementation concepts.
** Preferred Qualifications
*** Experience with synthesis, place and route, and timing analysis.
* Knowledge of low-power design techniques and PPA optimization.
* Programming experience with Perl, Tcl, and/or Python.
* Familiarity with ASIC/SoC physical design flows and EDA tools.
* Experience from coursework, research, or projects in VLSI or semiconductor design.## Job Type:Student / Intern##

Shift: Shift 1 (United States of America)## Primary

Location:

US, California, Folsom## Additional Locations:## Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.#### Position of TrustN/A## Benefits We offer a total compensation package that ranks among the best in the industry.

It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the .Annual Salary Range for jobs which could be performed in the US: $- USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Our standard…