Intern - Gen HBM Platform Arch Folsom, California, Posted

## Intern - Next Gen HBM Platform Arch Folsom, California, United States of America
** Our vision is to transform how the world uses information to enrich life for
* all*.
** Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

The HBM Platform Architecture team defines the electrical, thermal, and power-delivery architectures that enable Micron's next-generation High Bandwidth Memory (HBM) solutions. Working closely with architecture, design, packaging, and technology teams, the organization drives innovation in signaling, power integrity, thermal management, and system optimization to support AI, high-performance computing, and data center applications.###As an HBM Platform Architecture Intern, you will contribute to the development of future HBM platforms by evaluating electrical, thermal, and power delivery architectures for advanced memory systems.

You will work alongside experienced architects to analyze design trade-offs, develop modeling tools, and investigate solutions that improve performance, power efficiency, reliability, and scalability for next-generation memory products.

Responsibilities
* Perform signaling and timing analysis for on-die and off-die interfaces across multiple system and packaging topologies.
* Develop and evaluate thermal models to analyze heat transfer, thermal performance, and design trade-offs in advanced memory systems.
* Analyze power delivery networks (PDNs), including IR-drop, electromigration (EM), power integrity, and power grid optimization for advanced HBM architectures.
* Develop modeling, simulation, and automation tools to support power delivery, thermal analysis, and architecture evaluation activities.
* Collaborate with architecture, design, packaging, and technology teams to evaluate system-level trade-offs and support future HBM technology development.

Minimum Qualifications
* 0-2 years of relevant experience through internships, research projects, coursework, or academic projects in electrical engineering, VLSI design, signal integrity, power integrity, thermal analysis, semiconductor design, or related technical fields.
* Currently pursuing a Bachelor's, Master's, or PhD degree in Electrical Engineering, Electronics Engineering, Computer Engineering, Computer Science, or a related field.
* Coursework or project experience in analog design, I/O design, signaling, DRAM technologies, high-speed interfaces, packaging, or 2.5D/3D integration technologies.
* Understanding of electrical systems, signal integrity, power delivery, circuit analysis, or semiconductor design fundamentals.
* Ability to read and interpret technical specifications, datasheets, interface standards, and hardware documentation.
* Strong analytical, problem-solving, and technical communication skills.
* Experience using AI-enabled tools and large language models (LLMs) such as Copilot, Claude, ChatGPT, or similar technologies as part of engineering workflows, with the ability to validate and critically evaluate AI-generated outputs.

Preferred Qualifications
* Familiarity with Cadence EDA tools, MATLAB, thermal analysis tools, signal integrity tools, or related engineering software.
* Knowledge of semiconductor packaging, assembly processes, heterogeneous integration, or advanced packaging technologies.
* Experience with analog design, I/O design, timing analysis, signal integrity, or system-level electrical modeling through coursework, research, or project work.
* Experience with thermal modeling, computational analysis, power delivery analysis, IR-drop, electromigration (EM), or power integrity evaluations.
* Knowledge…