Senior Reliability Engineer - PDK & EDA Innovation
Listed on 2026-11-04
-
Engineering
Systems Engineer, Test Engineer, Quality Engineering, Electronics Engineer
Intel in Hillsboro, Oregon, seeks an Experienced Reliability Engineer to drive PDK design rules and collateral for reliability across advanced silicon and packaging technologies.
You will partner with internal teams and EDA vendors to deliver robust PDK/TFM content, perform benchmarking, and develop IP ecosystems that enable industry-leading PDKs, design rules, and quality verification for customer designs on Intel technology.
Join us at Intel as our next Senior Reliability Engineer - PDK & EDA Innovation in Folsom, CA, United States.
Join Intel and contribute to our ongoing work.
Take a moment to read everything above and see whether this role is right for you.
This posting is for the Senior Reliability Engineer - PDK & EDA Innovation role at Intel, based in Folsom, CA, United States.
We are looking to fill the Senior Reliability Engineer - PDK & EDA Innovation position at Intel in Folsom, CA, United States.
(If this job is in fact in your jurisdiction, then you may be using a Proxy or VPN to access this site, and to progress further, you should change your connectivity to another mobile device or PC).