Senior RTL-to-GDS Physical Design Engineer; 3nm FinFET
Listed on 2026-11-04
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Engineering
Electronics Engineer, Hardware Engineer
Lance Soft, Inc. is seeking an experienced ASIC Physical Design engineer to own end-to-end RTL-to-GDS flows, with strong hands-on experience in GDSII/STA, clock tree synthesis (CTS), timing closure and signoff, and robust RTL block implementations.
Preference for candidates with 3nm FinFET exposure, advanced-node semiconductor projects, and backgrounds from Broadcom, Google, or Intel. The role is contract-based with an extension possibility up to 1 year 3 months.
This is a genuine role to take on the Senior RTL-to-GDS Physical Design Engineer (3nm FinFET) role at Lance Soft, Inc.
The Senior RTL-to-GDS Physical Design Engineer (3nm FinFET) position in the Engineering field is open for applications.
We have an opening for a Senior RTL-to-GDS Physical Design Engineer (3nm FinFET) in Folsom, CA, United States within Engineering.
This role, Senior RTL-to-GDS Physical Design Engineer (3nm FinFET) at Lance Soft, Inc., could be your next opportunity.
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