Senior SoC DFT Engineer – HBM Test Architect
Listed on 2026-11-04
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Engineering
Test Engineer, Hardware Engineer, Electronics Engineer, Systems Engineer
Micron Technology in California is seeking an experienced design-for-test (DFT) lead for high‑bandwidth memory (HBM) SoC base‑die designs. You will own DFT architecture, implement scan, MBIST/LBIST, and JTAG, and collaborate with RTL, synthesis, and physical design to enable manufacturability and silicon bring‑up.
The role emphasizes early DFT definition, CDC checks, ATPG readiness, and cross‑group reviews, with mentoring for engineers and contributions to future HBM generations.
We are looking to fill the Senior SoC DFT Engineer – HBM Test Architect position at Micron Technology in Folsom, CA, United States.
The Senior SoC DFT Engineer – HBM Test Architect role at Micron Technology is now open for applications in Folsom, CA, United States.
Join us at Micron Technology as our next Senior SoC DFT Engineer – HBM Test Architect in Folsom, CA, United States.
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