Intern Generation HBM Architecture

Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

The Memory Systems Architecture team defines the next generation of High Bandwidth Memory (HBM) solutions that power artificial intelligence, high-performance computing, and data center applications. The team drives architectural innovation across memory systems, controllers, interfaces, and reliability features to deliver industry-leading performance, scalability, and efficiency for future computing platforms.

As a Memory Systems Architecture Intern, you will contribute to the architecture and microarchitecture development of future HBM products. You will work alongside experienced architects to evaluate new memory features, analyze architectural trade‑offs, develop performance models, and explore solutions that improve memory performance, reliability, and efficiency for AI and high-performance computing workloads.

• Research and evaluate next-generation HBM architecture and microarchitecture features, including memory scheduling, refresh management, reliability features, thermal behavior, and memory controller interactions.
• Develop and enhance performance models, simulators, and analytical tools using Python, C++, or similar technologies to assess architectural trade‑offs and system performance.
• Analyze workload behavior, simulation results, and architectural data to provide recommendations for future HBM product development.
• Utilize AI‑assisted engineering tools and workflows to accelerate software development, specification analysis, data exploration, and technical documentation while validating outputs using sound engineering judgment.
• Collaborate with architecture, design, memory controller, and cross‑functional engineering teams to support feature definition, design reviews, specifications, and roadmap development.

• 0-2 years of relevant experience through internships, research, academic projects, publications, or coursework in computer architecture, memory systems, VLSI, semiconductor design, or related technical fields.
• Currently pursuing a Bachelor's, Master's, or PhD degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• Coursework or project experience in computer architecture, memory hierarchies, DRAM technologies, interconnects, or hardware system design.
• Programming experience with Python and at least one of the following: C++, System Verilog, or similar engineering languages.
• Ability to read and interpret technical specifications, standards documentation, datasheets, or hardware interface definitions.
• Strong analytical, problem‑solving, written, and verbal communication skills.
• Experience utilizing AI coding assistants and large language models (LLMs) such as Git Hub Copilot, Claude, ChatGPT, or similar technologies as part of engineering workflows.

• Experience with memory or system simulation environments such as Ramulator, DRAMSim, gem5, or related architectural modeling tools.
• Knowledge of HBM, DDR, LPDDR, GDDR, memory controller architectures, or memory subsystem design.
• Familiarity with memory reliability and availability concepts, including ECC, repair mechanisms, refresh algorithms, or RAS features.
• Experience with System Verilog, digital design, RTL development, or verification methodologies.
• Experience applying AI tools to software development, data analysis, technical research, document analysis, workflow automation, or agentic engineering workflows.
• Understanding of AI training,…