Cache DFT Verification Engineer

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You will utilize your technical expertise to assist in the verification of AMD’s next‑generation CPU microprocessors.

You will maintain and enhance existing verification test benches to test cache functionality, including DFT features such as MBIST. You will work on related projects and/or assignments as needed to meet team goals; you will write and execute detailed test plans; you will develop high‑quality and efficient solutions, while collaborating effectively with cross‑functional teams; you will interface with architects and RTL designers.

Great opportunity to be involved in all phases of the project from specification to working with silicon validation teams.

A successful person in this role would possess good written and communication skills and would be able to work in a collaborative team environment working with architects, RTL designers, physical‑design, and silicon validation teams. At this level, you would need to demonstrate ownership, initiative, and the ability to influence technical outcomes with excellent time‑management skills.

• Perform Functional and Design for Test feature verification of high‑speed Microprocessor designs, including development of infrastructure, directed and random test suites at behavioral RTL and gate design levels across SoC, Core and block hierarchies.
• Develop environments, infrastructure, and test plans to accommodate both full chip and stand‑alone block‑level verification and debug capabilities using simulation tools, debug tools and programming skills, based on in-depth understanding of the architecture and HDL/logical design of the microprocessor.
• Participate in development of formal verification techniques.
• Develop an automated regression infrastructure setup for functional verification of highspeed microprocessor designs.
• Collaborate with a dedicated team of engineers to define and verify DFT microarchitecture for AMD CPUs.
• Work with product test teams during test bring up phase of the product.
• Based on thorough understanding of the design architecture, develop, run and debug x86 assembly based directed tests and random exercisers to validate functionality and testability operation of the microprocessor design leveraging C/C++/Perl/assembly programming, logic design and simulation skill set.
• Resolve all simulation discrepancies and assertion responses for both behavioral and gate level logic models.
• Measure and analyze coverage terms, address exposed weaknesses to meet design/project quality objectives.
• Develop infrastructure for pattern generation used in post silicon device validation and characterization.
• When presented with post‑silicon issues, replicate design responses using pre‑silicon infrastructure and provide debug expertise to ensure complete validation and characterization success.
• Coordinate with cross‑functional teams to meet project deliverables and manage dependencies with cross‑discipline/site RTL, DFT and Implementation design teams along with product manufacturing teams.

• Prior experience with verification techniques of microprocessors/ASIC designs.
• Demonstrated expertise with Verilog HDL.
• Proven programming proficiency in x86 assembly, C/C++ and Perl, and Ruby languages along with strong logic simulation competence.
• Demonstrated solid understanding of modern computer architecture including thorough DFT feature knowledge with JTAG‑1149.x, Memory, Logic and I/O…