Level Floor Planner Engineer – Physical Design Implementation

Overview

We are working with a leader in high speed data center networking and AI applications. They are currently seeking a Floor Planner Engineer to work on Physical Design Implementation for AI ASICs
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The ideal candidate will have a BSEE and 6+ years of industry experience in Physical Design implementation. This person will be responsible for top-level floor planning and interface internally with SoC and Interposer development, packaging, analysis, STA (static timing analysis), and IP while maintaining an aerial or top-level view of the entire physical design implementation process. Other than the technical attributes of the position, we are looking for someone who can effectively communicate with the customer, especially when the customer is being unrealistic about final designs (i.e. we need an effective communicator who doesn’t have a problem challenging the customer).

• Top-level floor planning and interface with SoC and Interposer development, packaging, analysis, STA, and IP.
• Maintain an aerial or top-level view of the entire physical design implementation process.
• Communicate with customers, including challenging them when final designs are unrealistic.

• Ideally a BSEE with 6-20 years of experience in Physical Design Implementation.
• Experience with Place and Route, Static Timing Analysis, etc., and willingness to adapt to a broader-level role.
• Experience with Physical Design tools (Cadence Virtuoso highly preferred; Synopsys also considered).
• Experience scripting using Python, TCL, and Linux.