Gen Core RTL Power, Clocking & Reset Engineer

AMD is seeking an experienced RTL design engineer to own power management, clocking, and reset RTL for Core Complex designs within the Core Complex Cache Hierarchy team. You will collaborate across Architecture, Physical Design, Verification, and Design-for-Test groups to deliver high-performance RTL and drive next-generation cores with aggressive schedules.

The candidate should have a strong background in Digital RTL Design, Verilog HDL, and scripting, and be capable of mentoring engineers

We are seeking a motivated Next-Gen Core RTL Power, Clocking & Reset Engineer to join AMD in Fort Collins, CO, United States.

Our group is growing, and we are hiring a Next-Gen Core RTL Power, Clocking & Reset Engineer in Fort Collins, CO, United States.

This opportunity is for the Next-Gen Core RTL Power, Clocking & Reset Engineer role at AMD.