Sr DFT​/ATPG Engineer–Mixed-Signal IP

ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward.

Join us and, together, we’ll advance your career.

THE ROLE:

The Scan ATPG Engineer will own scan architecture and validation strategy for analog and mixed-signal intellectual property (IP). This role is responsible for delivering production-quality test patterns and supporting silicon bring-up and debug of those patterns. The engineer will collaborate across analog design, digital design, verification, DFT, physical design, product engineering, and test engineering teams to deliver robust, manufacturable solutions that achieve high test quality.

THE PERSON:

The ideal candidate brings strong technical judgment, ownership, and a collaborative approach to solving complex engineering challenges. They communicate technical information clearly to different audiences and work effectively across functions to build alignment around practical technical solutions. They are curious, adaptable, and committed to continuous learning and improvement, with the ability to lead technical initiatives and contribute effectively within a collaborative engineering environment.

KEY RESPONSIBILITIES:

Define and document scan architectures for analog and mixed-signal IP, considering test coverage, implementation complexity, timing, power, area, and integration requirements.

Develop and maintain ATPG models for custom digital, analog-interface, and mixed-signal circuitry to enable accurate fault modeling and pattern generation.

Validate scan-stitched gate-level netlists, including scan-chain connectivity, test-mode controls, clocks, resets, constraints, and cross-domain behavior.

Analyze, debug, and improve test coverage to achieve appropriate coverage targets across multiple fault models, including stuck-at and transition-delay faults.

Perform zero-delay and SDF-annotated gate-level simulations of ATPG patterns; identify and resolve simulation failures, timing issues, X-propagation, and model or netlist mismatches.

Own the generation, validation, documentation, delivery, and lifecycle management of production test patterns.

Partner with product and test engineering teams to support pattern deployment, silicon bring-up, yield learning, failure analysis, and post-silicon debug.

Collaborate with cross-functional teams to identify and resolve testability issues and contribute to improvements in architecture, methodology, automation, and quality.

PREFERRED EXPERIENCE:

Experience with scan design, ATPG, fault simulation, coverage analysis, and pattern validation for complex IP or SoC designs.

Experience applying DFT methodologies to analog and mixed-signal IP, including modeling custom circuitry and interfaces for ATPG.

Experience with industry-standard ATPG, gate-level simulation, waveform-debug, and DFT verification tools.

Knowledge of multiple fault models, such as stuck-at, transition-delay, cell-aware, bridging, or comparable advanced defect-oriented models.

Experience identifying and resolving scan-chain, netlist, constraint, clocking, reset, timing, and X-propagation issues.

Knowledge of zero-delay and SDF-annotated simulation flows and production pattern formats.

Experience supporting silicon bring-up, production test deployment, yield learning, post-silicon failure analysis, or closely related activities.

Programming or scripting…