Hybrid Senior ASIC Physical Design Engineer
Listed on 2026-10-15
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Engineering
Systems Engineer, Hardware Engineer, Electronics Engineer
Hewlett Packard Enterprise is seeking a Senior ASIC Physical Design Engineer in Colorado for a hybrid role requiring on-site 2 days per week. You will contribute to synthesis, timing, and signoff for complex ASICs, collaborating with cross-functional teams across architecture, DFT, and signal integrity.
The role emphasizes physical-design-aware methodologies and scalable flows. Required 6–10 years in ASIC/VLSI with expertise in timing closure, STA, and EDA tools; strong scripting in Python or
The Hybrid Senior ASIC Physical Design Engineer role at Hewlett Packard Enterprise Company is now open for applications in Fort Collins, CO, United States.
We aim to respond to suitable candidates as soon as possible.
Full responsibilities and requirements are described in the listing above.
Learn more about the Hybrid Senior ASIC Physical Design Engineer role in the description above.
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