Hybrid VLSI Logic Design Intern; SystemVerilog
Listed on 2026-10-19
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Engineering
Hewlett Packard Enterprise offers a VLSI Logic Design Intern position in Colorado with a hybrid work arrangement requiring about 2 days per week in an HPE office. The role focuses on VLSI/RTL design using System Verilog, asserting properties with SVAs, and applying Formal Verification to ensure correctness.
The intern will also develop coverage metrics, write scripts in Python/TCL/Perl, and collaborate with DV/Arch/Design/FW teams.
We are seeking a motivated Hybrid VLSI Logic Design Intern (System Verilog) to join Hewlett Packard Enterprise Company in Fort Collins, CO, United States.
The position is based in Fort Collins, CO, United States.
This opportunity is part of our work in Engineering, Other.
The advertised compensation is 48.000 - 56.000.
We aim to respond to suitable candidates as soon as possible.
Full responsibilities and requirements are described in the listing above.
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