ASIC Design - Floorplan Engineer

ASIC Design
- Floorplan Engineer### ASIC Design
- Floorplan Engineer Apply:
USA-Colorado-Fort Collins-4380 Ziegler Road:
Full time:
Posted Today:
R027510
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* Job Description:

** Be part of the Custom Silicon Design Team within Broadcom’s ASIC Products Division in beautiful Fort Collins, Colorado. Join a world-class engineering group developing custom CMOS ASICs for cutting-edge AI, Cellular, Networking, Computing, and Storage products. This Floorplan Engineer role focuses on chip-level physical architecture and integration for advanced ASICs operating at speeds exceeding 1 GHz, from concept through production.

The position provides hands-on experience with the latest 3 nm and smaller process nodes, defining and optimizing the overall die layout, including partitioning, hierarchy, and placement of major functional blocks, memories, and I/O structures for AI, computing, and networking SoCs.
** Key Responsibilities
*** Define and optimize top-level floorplan architecture, including die size estimation, hierarchy definition, and partitioning.
* Drive macro placement, power grid design, clock distribution planning, pin placement, and feed through optimization.
* Collaborate closely with RTL, timing, and packaging teams to balance performance, power, and area (PPA) targets.
* Lead top-level timing closure, congestion analysis, and ECO implementation to ensure clean tapeout readiness.
* Coordinate with block owners and integration teams for smooth block-level to top-level convergence.
* Support cross-functional design integration, providing guidance and technical support to internal and external partners.
* Apply a deep understanding of block PnR, timing closure, physical verification, and IR/EM analysis to achieve signoff-quality results.
* Contribute to design flow automation and methodology development for advanced process technologies.
** Technical Skills / Background
*** Strong foundation in VLSI design principles and ASIC physical design fundamentals.
* In-depth experience with floor planning, die partitioning, and hierarchical design.
* Working knowledge of PLLs, clock networks, power delivery, and timing-critical structures.
* Proven ability to drive PPA optimization through innovative layout and planning strategies.  
** Coding & Tool Proficiency
*** Strong experience with TCL scripting and Linux environments is required.
* Proficiency in Python, Perl, or Ruby is preferred.
* Experience with Cadence or equivalent physical design tools is highly desirable.  
** Collaboration and Leadership
*** Excellent communication, organizational, and problem-solving skills.
* Ability to work effectively with customers and cross-functional teams across global sites and time zones.
* Skilled at organizing and presenting large data sets, managing multiple priorities efficiently.
* Exercises independent judgment and strong engineering insight in defining methods, techniques, and evaluation criteria.
* Provides technical leadership, mentors others, and leads execution of new initiatives.  
** Education and Experience
*** BS in Electrical or Computer Engineering with 12+ years of relevant experience, or
* MS in Electrical or Computer Engineering with 10+ years of relevant experience.  
** Compensation and Benefits
** The annual base salary range for this position is USD To USD    As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly…