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Senior IC Verification Engineer - SystemVerilog​/UVM Expert

Listing for: Broadcom Inc.
Full Time position Listed on 2026-11-11
Job specializations:
  • Engineering
    Test Engineer
Salary/Wage Range or Industry Benchmark: 110000 - 176000 USD Yearly USD 110000.00 176000.00 YEAR

Job Description & How to Apply Below

The ASIC Product Division in Broadcom is seeking qualified individuals to contribute to SoC and IP development programs. You will join a high‑performance design team delivering state‑of‑the-art subsystems for AI and storage chips.

Responsibilities include building verification environments with System Verilog and UVM, designing verification classes, implementing coverage and assertions, and developing random test cases.

This role, Senior IC Verification Engineer
- System Verilog/UVM Expert at Broadcom Inc., could be your next career step.

This opportunity is part of our work in Engineering.

The advertised compensation is 110..

We aim to respond to suitable candidates as soon as possible.

Full responsibilities and requirements are described in the listing above.

Learn more about the Senior IC Verification Engineer
- System Verilog/UVM Expert role in the description above.

We appreciate your interest in this position.

Position Requirements

10+ Years work experience
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