Design Verification Engineer - UVM & Xcelium Expert

A leading semiconductor company in Fremont, CA is seeking a Design Verification Engineer to develop UVM-based verification environments and collaborate closely with RTL and mixed-signal engineers. Candidates should have 3+ years of experience in design verification and proficiency in System Verilog and Cadence Xcelium.

This role offers an opportunity to work on cutting-edge semiconductor projects in a dynamic environment.
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