Design Verification Engineer - UVM​/Xcelium Expert

A leading semiconductor firm is seeking a Design Verification Engineer to join their onsite team in Fremont, California. The role involves developing UVM-based verification environments, executing tests for digital designs, and collaborating with design teams. Candidates should have 3+ years of relevant experience, proficiency in System Verilog and UVM, and skill in using Cadence Xcelium. This full-time position offers an exciting opportunity to work on cutting-edge projects in a dynamic environment.
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