Sr. Staff Engineer – Processor Verification and Compiler Validation

Enphase Energy is a global energy technology company and a leading provider of solar, battery, and electric vehicle charging products. Founded in 2006, our innovative microinverter technology revolutionized solar power, making it a safer, more reliable, and scalable energy source. Today, the Enphase Energy System enables users to make, use, save, and sell their own power. Enphase is also one of the most successful and innovative clean energy companies in the world, with more than 80 million products shipped across 160 countries.

Join our dynamic teams designing and developing next-gen energy technologies and help drive a sustainable future!

Enphase is looking for an experienced Verification Engineer to help validate a custom RISC-V VLIW processor architecture that powers next‑generation digital control systems for energy conversion products. You will be responsible for ensuring deterministic and correct operation across the entire compute stack, including custom hardware pipelines, proprietary instruction set extensions, compiler-generated execution schedules, and closed-loop control applications.

This role is ideal for an engineer who thrives at the intersection of processor architecture, hardware verification, compiler technology, and control systems. You will work closely with architecture, RTL, verification, compiler, firmware, and control algorithm engineers to develop comprehensive verification methodologies that ensure safety‑critical control loops execute with predictable timing and flawless functional correctness.

As part of this role, you will also contribute to system‑level mixed‑signal verification environments that combine RTL simulation, real‑number modeling, power stage models, and analog simulation platforms to validate real‑world control‑loop behavior.

• Develop and execute verification strategies for a custom RISC‑V VLIW processor architecture and associated instruction set extensions.
• Create and maintain
  
  System
  
  Verilog‑based verification environments, assertions, checkers, scoreboards, coverage models, and regression infrastructure.
• Verify pipeline correctness, instruction scheduling behaviour, memory subsystem interactions, exception handling, and architectural compliance.
• Develop trace‑based validation methodologies to ensure deterministic execution timing for real‑time control applications.
• Analyze execution traces, instruction schedules, waveform data, and performance metrics toidentifyroot causes of hardware or compiler issues.
• Collaborate with compiler engineers tovalidatecode generation, instruction scheduling, optimization behaviour, and ISA featureutilization.
• Drive hardware/software co‑verification efforts spanning RTL, compiler tool chains, firmware, and system‑level applications.
• Contribute to mixed‑signal verification environments integrating:
• RTL simulation
• System Verilog Real  Number Modeling (RNM)
• Analog simulation platforms such as NL5
• C/C++ models of power conversion stages and plant models
• Python‑based analysis and automation frameworks
• Validate closed‑loop control behaviour, timing determinism, fault handling, and system‑level interactions between digital control algorithms and analog power stages.
• Support verification automation, regression analysis, debug tooling, and continuous improvement of verification methodologies.
• Document verification strategies, debug findings, and architectural insights to support long‑term product quality and organisational knowledge sharing.

• PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field with 5+ years of relevant industry experience, OR Master's degree with 8+ years of relevant industry experience.
• Strong understanding of processor…