Senior PCIe Subsystem RTL Architect

TYLsemi, Inc. is seeking a Principal PCIe Sub-system Front-end RTL lead to own the PCIe microarchitecture for high‑performance compute chiplets.

You will drive integration of PCIe IP, define lane configurations, and oversee TL pipelines, VC and flow‑control, while collaborating with firmware and physical design teams. You will mentor RTL engineers, define verification plans with DV teams, and engage with customers on interface bring‑up.

This role, Senior PCIe Subsystem RTL Architect at TYLsemi, could be your next career step.

Are you ready to take on the Senior PCIe Subsystem RTL Architect role at TYLsemi?

We would love to welcome a new Senior PCIe Subsystem RTL Architect to our group in San Jose, CA, United States.

For the Senior PCIe Subsystem RTL Architect position at TYLsemi, we are reviewing applications now.