Physical Design Engineer

Experience:

12+ Years

• -Execute end-to-end Physical Design, Synthesis, Physical Verification, and Timing Closure activities.
• -Setup and synthesize RTL designs.
• -Perform timing closure using various methodologies and strategies, including top-level STA.
• -Conduct EM/IR analysis.
• -Execute Place & Route (P&R).
• -Develop and optimize Clock Tree Synthesis (CTS), including custom clock trees, insertion delay reduction, and skew balancing.
• -Perform floor planning and layout activities, preferably with top-level floor planning expertise.
• -Contribute to flow and methodology development.
• -Collaborate closely with IC Design and RTL Engineering teams.

• -Strong experience with Cadence Innovus.
• -Expertise in the complete Physical Design cycle from RTL to Tape-out.

• -Synthesis
• -Static Timing Analysis (STA)
• -Timing Closure
• -Place & Route
• -Clock Tree Synthesis (CTS)
• -Floor planning
• -Physical Verification
• -EM/IR Analysis
• -Strong TCL and/or PERL scripting skills.
• -Proficiency with industry-standard EDA tools.
• -Excellent communication and collaboration skills.

• -Bachelor's Degree in Electrical Engineering, Electronics Engineering, or related field.

• -Deep expertise in top-level floor planning and STA.
• -Proven success delivering complex ASIC/SoC designs through tape-out.