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ASIC Front-End Designer Source RTL & Tapeout

Job in Genf, Geneva, Switzerland
Listing for: Physics World
Full Time position
Listed on 2026-07-26
Job specializations:
  • Engineering
    Hardware Engineer, Systems Engineer
Salary/Wage Range or Industry Benchmark: 63192 - 69516 CHF Yearly CHF 63192.00 69516.00 YEAR
Job Description & How to Apply Below
Position: ASIC Front-End Designer - Open-Source RTL & Tapeout
Location: Genf

CERN is seeking a talented engineer to design, simulate, and verify the digital front-end for the next-generation ASICs used in radiation monitoring and safety-critical systems. You will prepare RTL for tapeout, work with open-source EDA tools, and assist after-fabrication bring-up and validation.

Ideal candidates have experience with RTL to GDSII, floor planning, and hardware debugging. A hybrid work model is offered with opportunities for professional growth within CERN's HSE-TS-IMS division.

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