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ASIC Digital Designer Source RTL to Tapeout
Job in
Genf, Geneva, Switzerland
Listed on 2026-07-27
Listing for:
CERN
Full Time
position Listed on 2026-07-27
Job specializations:
-
Engineering
Hardware Engineer, Electronics Engineer
Job Description & How to Apply Below
Location: Genf
CERN designs, develops, and operates particle accelerators and experiments. You will join the HSE-TS-IMS Section to design, verify, and bring up the next-generation ASIC front-end using open-source EDA tools, with a focus on RTL to GDSII work.
The role involves collaboration across SoC, analogue, and verification teams in a hybrid work setting. Requirements include hands-on experience with Yosys/OpenROAD/Libre Lane, RTL design in Verilog/System Verilog, and knowledge of RISC-V.
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