Digital ASIC Designer (EP-ESE-ME-2026-134-GRAP

Digital ASIC Designer (EP-ESE-ME--GRAP)

• Full-time
• Compensation: CHF 6,372 - CHF 7,004 - monthly

Join CERN’s EP-ESE-ME section in the development of a radiation-tolerant microcontroller ASIC for use in future particle physics detectors and accelerator systems. Operating in highly challenging radiation environments, these systems require robust and reliable embedded electronics.

The project is based on an open-source RISC‑V processing core and the CERN SOCRATES (System‑On‑Chip Radiation‑Tolerant Ecosystem) framework for fault‑tolerant SoC design. The successful candidate will contribute to the full development cycle, from requirements definition and system architecture to implementation, verification, and post‑silicon validation.

Your responsibilities:

• Analyse application requirements across CERN’s accelerator complex and particle physics detector systems to define technical specifications for the microcontroller ASIC.
• Contribute to the architecture, design, and validation of a radiation‑tolerant microcontroller ASIC implemented in 65 nm or 28 nm CMOS technology.
• Support the definition of the SoC architecture, including the selection and configuration of an appropriate RISC‑V processing core.
• Design, integrate, and validate peripheral IP blocks within the CERN SOCRATES framework.
• Apply fault‑tolerant design methodologies, including triple modular redundancy (TMR) and single‑event upset (SEU) mitigation techniques.
• Participate in design verification activities and physical implementation, from RTL development through to tapeout.
• Contribute to post‑silicon testing, characterisation, and validation following chip fabrication.

Your profile:

• Strong understanding of digital logic design.
• Solid experience with digital IC design and RTL development (Verilog/System Verilog).
• Familiarity with standard ASIC design flows (synthesis, place and route, timing closure).
• Knowledge of RISC‑V architecture and its ecosystem.
• Experience with microcontroller‑based embedded systems development, including firmware programming in C and peripheral interfacing.

Skills:

• RTL design and simulation (Verilog / System Verilog).
• Familiarity with the digital ASIC design flow, including synthesis, place‑and‑route, timing closure, and sign‑off activities.
• Knowledge of fault‑tolerant design techniques and radiation effects in CMOS circuits is an asset.
• Microcontroller embedded systems development (firmware in C, peripheral interfacing, bare‑metal programming).
• Scripting and automation (Python or equivalent).
• Linux/Unix working environment.
• Curiosity and willingness to learn in a multidisciplinary environment.
• Ability to work independently as well as within a team.
• Spoken and written English, with a commitment to learn French.
• You have a professional background in Electronics Engineer (or a related field) and have either:
  • a Master’s degree with 2 to 6 years of post‑graduation professional experience;
  • or a PhD with no more than 3 years of post‑graduation professional experience.
• You have never had a CERN fellow or graduate contract before.

Contract duration: 24 months, with a possible extension up to 36 months maximum.

Working hours:

40 hours per week

Job flexibility:
Fully Onsite

Job reference: EP‑ESE‑ME‑2026‑134‑GRAP

Field of work:
Electrical or Electronics Engineering

Benchmark job: 200050 - Electronics Engineer

• A monthly stipend between Swiss Francs per month (tax free) depending on your degree.
• 30 days of paid leave per year plus 2 weeks annual closure.
• Coverage by CERN’s comprehensive health insurance scheme (for yourself, your spouse and children), and membership of the CERN Pension Fund.
• Family, child and infant monthly allowances depending on your individual circumstances.
• A relocation package (installation grant and travel expenses) depending on your individual circumstances.
• Possibility to extend your contract up to 36 months.
• On‑the‑job and formal training including language classes.

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