Senior SoC RTL Design Engineer
Listed on 2026-10-15
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Engineering
Hardware Engineer, Test Engineer, Electronics Engineer, Systems Engineer
Synopsys Inc. in Gilbert, AZ is seeking an RTL engineer to turn RTL specifications into robust Verilog/System Verilog designs for block‑level architectures, including state machines, pipelines, FIFOs, and memory controllers.
You will ensure clean synthesis and meet timing goals across the ASIC/FPGA flow. You will collaborate with verification, DFT, and physical design teams globally, write automation scripts (Python/Tcl), and participate in design reviews to communicate tradeoffs and decisions.
We invite applications for the Senior SoC RTL Design Engineer position located in Gilbert, AZ, United States.
We are seeking a motivated Senior SoC RTL Design Engineer to join Synopsys Inc in Gilbert, AZ, United States.
Consider building your career as a Senior SoC RTL Design Engineer at Synopsys Inc.
The Senior SoC RTL Design Engineer position in the Engineering field is open for applications.
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