Senior Digital Verification Engineer

## Senior Digital Verification Engineer Apply locations:
Glasgow:
Gratkorntime type:
Full time posted on:
Posted 8 Days Agojob requisition :
R-Within the
** Crypto & Security Competence Center**, you will be part of a dedicated team focusing on research and development for future security applications, ranging from hardware IP design to strong end‐to‐end security solutions.

For our
** Security Design team in Glasgow, UK**, we are looking for a highly motivated
** Digital Verification Engineer
** to join our team.

At this site, our engineers are actively involved in all aspects of security hardware design, delivering high‐end security IP into multiple NXP business lines and a variety of market segments, including
** Automotive, Microcontrollers, Banking / Mobile and Connectivity**. Engineers contribute throughout the full product lifecycle, from requirements capture and architectural definition through development and verification, to test‐chip and silicon validation.
** Your Responsibilities
*** Responsible for verifying functional behaviour of complex digital hardware architectures
* Creating, reviewing, and maintaining verification plans, and tracking verification progress.
* Specifying and developing verification strategies, tests, and environments for security features and hardware co‐processors.
* Working with emerging verification methodologies and introducing them into existing verification flows.
* Mentoring junior team members in best practices, driving technical excellence and consistency across teams.
** Your Profile
*** BSc., or MSc., degree in Electronics or Electrical Engineering.
* Strong hands-on experience with
** System Verilog
* * for testbench development and verification.
* Proven expertise in
** UVM (Universal Verification Methodology)**, including component creation, sequences, drivers, monitors, and scoreboards.
* Solid understanding and practical use of
** Constrained Random Verification
** techniques.
* Experience with
** Metrics‐Driven Verification**, including functional coverage and verification planning.
* Ability to write
** System Verilog Assertions (SVA)
** for protocol and design checking.
* Demonstrated success in achieving
** Coverage Closure
** across functional and code coverage metrics.
* Experience analysing coverage results and refining test strategies to close gaps.
* Strong debugging skills across simulations and complex verification environments.
* Knowledge of Formal Verification methods would be advantageous.

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