Senior SystemVerilog​/UVM Verification Engineer - Pre-Silicon

A global staff augmentation firm is seeking a Verification Engineer in California to perform pre-silicon functional verification of high-performance SoCs. The ideal candidate should have strong expertise in UVM and System Verilog, and possess a Bachelor’s degree in a relevant field. Responsibilities include developing test benches, debugging complex designs, and automating verification flows. Competitive salary and an equal opportunity work environment offered.
#J-18808-Ljbffr