Hardware Security Engineer - Hyperscaler Security Hybrid

The Hardware Security Engineer role will support Cisco’s Hyperscaler Security efforts by helping ensure Cisco’s next-generation platforms and custom hyperscaler hardware architectures meet security, trust, and resilience expectations. The position includes system-to-silicon security analysis, translating standards into engineering guidance, and running concurrent security and compliance work streams.

• Assess system-level hardware designs, including schematics, board architectures, and component datasheets, to identify threat vectors, vulnerabilities, and compliance gaps.
• Interpret, apply, and establish requirements aligned with emerging standards and compliance frameworks, including NIST SP 800-193 (Platform Firmware Resiliency),
  NSA CNSA 2.0 (Post-Quantum Cryptography / CNSA Suite), the EU Cyber Resilience Act (CRA), and internal Hardware Cisco Secure Development Lifecycle (HW-CSDL) mandates.
• Provide technical advisory support by producing clear, actionable security requirements and architectural design guidance for product teams, hardware design engineers, firmware/BIOS teams, and third‑party vendors.
• Develop hardware security requirements, review checklists, threat models, compliance white papers, and engineering specifications for internal and external audiences.
• Participate in and manage multiple concurrent security evaluations, design reviews, and compliance work streams across diverse hardware programs.

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field, plus 7+ years of relevant experience. Substitutions:
  Master’s with 4+ years
  , or PhD with 1+ year
  .
• Background in hardware development, including experience reading and interpreting system‑level schematics, block diagrams, component datasheets, PCB design or review, or register‑level hardware documentation.
• Background in hardware security fundamentals, including Hardware Root of Trust (RoT),
  Secure Boot
  , hardware and firmware resiliency, cryptographic primitives (symmetric/asymmetric encryption, hashing, digital signatures), and secure key storage.

• Experience crafting, implementing, or evaluating hardware‑rooted attestation architectures and device identity mechanisms such as SPDM and TCG DICE
  .
• Experience with hyperscaler and cloud platform architectures (for example,
  OCP specifications
  , OpenBMC
  , Caliptra
  , Open Titan
  , OpenPRoT
  ).
• Experience implementing industry standard security IP or developing novel hardware security solutions (examples include FPGA bitstream security
  , secure microcontroller architectures,
  HW RoT
  , and bus encryption).
• Experience with hardware threat modeling or hardware security analysis, including fault injection, side‑channel analysis, and JTAG/debug security.
• Background in hardware security frameworks and standards such as NIST SP 800-193
  , NSA CNSA 2.0,
  TCG DICE / TPM
  , or global cybersecurity regulations including the EU CRA
  .

Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related technical field.

Research Triangle Park (RTP), NC with a hybrid work model. Onsite requirement: 3 days per week.

• Salary range: USD 132,800 to 259,100 per year.
• Starting salary range posted: $ to $.
• State‑specific full salary ranges:
  • New York City Metro Area: $ to $
  • Non‑Metro New York state & Washington state: $ to $

For quota‑based sales roles on Cisco’s sales plan, the ranges provided in this posting include base pay and sales target incentive compensation combined.

Expected to close on:
11/29/2026

• Medical, dental and vision insurance
• 401(k) plan with a Cisco matching contribution
• Paid parental leave
• Short and long‑term disability…