FPGA/RTL Design Engineer – III; W2 Job Hillsboro area,Oregon USA,Engineering

FPGA/RTL Design Engineer – III (W2 Only)

Contract

About Collabera
Collabera is the largest minority-owned Information Technology (IT) staffing firm in the U.S., with more than $525 million in sales revenue and a global presence that includes approximately 10,000 professionals across North America (U.S., Canada), Asia Pacific (India, Philippines, Singapore, Malaysia), and the United Kingdom. We support our clients with a strong recruitment model and a sincere commitment to their success, which is why more than 75% of our clients rank us amongst their top three staffing suppliers.

We are committed to exceeding our customer’s needs and ensuring our employees’ satisfaction. Our employees are the cornerstone of our success, and we strive to provide an enriching experience that promotes career growth and lifelong learning. Collabera has been recognized by Staffing Industry Analysts (SIA) as the “Best Staffing Firm to Work For” for four consecutive years since 2012. With over forty offices globally and a presence in seven countries, we provide staff augmentation, managed services, and direct placement services to Global 2000 Corporations.

Collabera is ranked among the top 10 IT staffing firms in the U.S., and we have experienced consistent growth over the past 24 years.

For more information about our latest job openings, visit

Awards and Recognitions
-- Staffing Industry Analysts: Best Staffing Firm to Work For )
-- Staffing Industry Analysts: Largest U.S. Staffing Firms )
-- Largest Minority Owned IT Staffing Firm in the US.

Location:
Hillsboro, OR

Duration: 4+ Months

Job Description

This is a senior RTL design engineer position. Primary responsibilities include:

Working with IP designers and DFx engineers to define and scope design requirements and develop specifications for testing a given IP on a test chip.

Implementing the specifications/design in RTL.

Collaborating with the pre-silicon verification team to develop test plans and verification collateral.

Working with the physical design team for floor-planning and timing convergence.

Supporting post-silicon validation teams to resolve silicon-level sightings.

Coordinating with IP designers and third-party IP vendors to define and develop specifications for evaluating/testing interoperability of soft IPs (e.g., DDR memory controllers) with Intel Hard IP.

Qualifications include:

Bachelor's or Master's degree in Electrical Engineering with at least 8+ years of relevant industry experience.
Experience with ARM-based SoC design, including AXI/ACE and APB bus protocols.
Proficiency in HDL design with Verilog/System Verilog.
Experience with ASIC and/or SoC design flows and methodologies, including CPF/UPF flows.
Familiarity with industry-standard RTL design, simulation, and formal verification tools.
Experience in synthesis and timing constraint development.
Scripting skills in Perl/Tcl.
Strong written and verbal communication skills for effective collaboration and influence within teams.

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FPGA​/RTL Design Engineer – III; W2

FPGA/RTL Design Engineer – III; W2