Senior Layout Designer

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Designs, implements, and verifies the layout design of test structures and circuits which enable the development of Intel's leading-edge silicon technologies. The test structures are tailored to model Quality and Reliability (QnR) parameters which are essential to the qualification life cycle for each technology.

You will have the opportunity to work with partners in Technology Development (TD), Design Technology Platform (DTP), and a world class team of QnR engineers to understand, define, and execute the requirements of new trailblazing Test Chips.

• Develop custom layout design of analog blocks, complex digital, mixed signal blocks, standard cell libraries, or memory compilers (e.g., bitcells, SRAMs, Register Files).
• Perform detailed physical array planning, area optimization, digital block synthesis, critical wire analysis, custom leaf, cell layout, and compiler assembly coding.
• Conduct complete layout verification including design rule compliance, SoC integration specs, electron migration, voltage drop (IR), self‑heat, ESD, and other reliability checks. Uses custom auto‑routers and custom placers to efficiently construct layout.
• Provide feedback to circuit design engineers for new feature feasibility studies and implement circuit enhancement requests.
• Develop and drive new and innovative layout methods to improve productivity and quality.
• Troubleshoot a wide variety of issues up to and including design and tool/flow/methodology issues used for layout design.

• Design, implement, verify, and support the enablement and adoption of hardware design tools, flows, and methodologies.
• Define methodologies for hardware development related to technology node and EDA tool enabling.
• Create and verify unique hardware designs, assemble design platforms, and integrate components into hierarchical systems to provide deployment coverage for end‑to‑end EDA tool testing on new technology nodes.
• Develop, test, and analyze engineering design automation tools, flow, and methodologies to improve efficiency and optimize power and performance.
• Support development and enhancement of platforms, databases, scripts, and tools flows for design automation.
• Build deep understanding of digital design, verification, structural and physical layout, full‑chip integration, power, performance clocking, and/or timing to enhance future TFM development.
• Collaborate with EDA vendors on defining and early testing of next‑generation design tools.

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

• Batch:
  Bachelor's degree in Electrical/Computer Engineering or related field and 6+ years of experience OR a Master's degree in Electrical/Computer Engineering or related field and 4+ years of experience OR a PhD in Electrical/Computer Engineering or related field and 2+ years of experience in:
• Layout design & Cadence Virtuoso

• 6+ years of experience in:
• CMOS VLSI design concepts, flows, and EDA tools
• Programming/scripting in C/C++, Python.
• UNIX/Linux operating systems.
• 8+ years of experience in layout design, Cadence Virtuoso Layout Suite, layout debug (DRC, LVS).
• 4+ years of experience in EDA Tools, Flows, and Methodology (TFM) development
• 1+ year of experience with Cadence SKILL programming languages.
• Experience leading and coordinating small/medium size group of layout designers.
• Strong initiative, analytical/problem solving skills, communication skills, team working skills, ability to multitask and be able to work with a diverse team located in different geos.

Experienced Hire

Shift 1 (United States of America)

US, Oregon, Hillsboro

US, Arizona, Phoenix

Intel Foundry strives to make every facet of semiconductor manufacturing state‑of‑the‑art while delighting our customers -- from delivering cutting‑edge silicon process and packaging…